Modern communication systems often employ signals with high peak to average power ratio (PAPR) to improve the spectral efficiency. The efficiency of traditional class-AB power amplifiers (PA) is however rapidly degraded when the output power is backed off from its maximum. The efficiency at back off may be improved by incorporating the power amplifier into special transmitter/PA architectures, such as Doherty, W. H. Doherty, “A New High Efficiency Power Amplifier for Modulated Waves,” Proceedings of the Institute of Radio Engineers, vol. 24, no. 9, pp. 1163-1182, September 1936, out -phasing or dynamic load modulation. Due to its relative simplicity and high performance, the Doherty PA is widely adopted in commercial applications.
The fundamental principle of Doherty operation is to modulate the impedance seen by the main transistor via active current injection using an auxiliary transistor. Based on this principle, the peak efficiency can be maintained both at peak power and at the average power level of the signal, e.g. at 6.5 dB back-off.
The classical Doherty configuration ideally consists of one class-B biased transistor, from here on referred to as the main transistor, and one class-C biased transistor, from here on referred to as the auxiliary transistor, combined with a quarter wave transformer. The auxiliary transistor's class-C bias is selected such that the required current profiles are achieved. This configuration provides the ideal maximum efficiency (78.5%) of the class-B biased main transistor and the ideal maximum efficiency (>78.5%) of the class-C biased auxiliary transistor at peak power level. At a selected output power back-off (OPBO) from the peak power level, the ideal maximum efficiency is provided for the main transistor, while the auxiliary transistor is turned off. Originally, Doherty described current profiles resulting in a second efficiency peak at 6 dB OPBO. Fortunately, the current profiles can easily be generalized such that the second efficiency peak can be placed at any desired back-off level, γ. This generalized form of the Doherty configuration will be denoted as the classical Doherty power amplifier (DPA).
The classical DPA requires the auxiliary transistor to be larger than the main transistor to reach the desired current profiles. For instance, for γ=6 dB, when fully utilizing the auxiliary transistor, the auxiliary transistor must be 1.27 times larger than the main transistor, and for γ=9 dB, the auxiliary transistor must be 2.10 times larger than the main transistor.
The class-C biasing of the auxiliary transistor, together with the effect of the intrinsic parasitics scaling in proportion to the transistor size, result in asymmetrical power splitting into the two transistors. For small signals, when the auxiliary transistor is turned off, the input power split can directly be translated into gain loss; when the auxiliary transistor turns off, the power injected into the auxiliary transistor will just be wasted. Moreover, if the power division ratio of a splitter is very uneven, the resulting transmission lines become very thin and/or thick, putting a practical limitation on the realization of the splitter. In some cases, even attenuators are used to achieve the right power division ratio, badly degrading the power added efficiency (PAE), as disclosed by Jangheon Kim, et al., “Optimum operation of asymmetrical-cells-based linear Doherty power Amplifiers-uneven power drive and power matching,” IEEE Transactions on Microwave Theory and Techniques, vol. 53, no. 5, pp. 1802-1809, May 2005.
A well-known method of reducing the small signal gain loss of the input power splitter is to make the auxiliary transistor larger than necessary and underutilize it. As the auxiliary transistor becomes bigger, the auxiliary bias approaches class-B bias. This isolated effect will result in a less asymmetrical input power split, but intrinsic parasitics scaling will lessen this effect severely. Even though an oversized auxiliary transistor DPA has somewhat lower combiner gain loss than a DPA with a fully utilized auxiliary transistor, substantial oversizing is often unpractical due to extrinsic parasitics and physical dimension constraints. Moreover, oversizing directly translates into higher cost. In real-life applications, a DPA with symmetrical or close to symmetrical transistors is often the preferred choice, as outlined in WO2015/055242 disclosing a symmetrical amplifier.
Other methods to improve the gain are to increase the main cell bias towards class-AB and/or reducing the size of the class-C cell without any compensation in the topology. Naturally, these solutions will violate the ideal operation of the circuit, significantly degrading the drain efficiency.
In power amplifier designs, PAE is one of the most important attributes; in order to reach high enough PAE, sufficient efficiency and gain is required. When approaching millimeter waves, low gain is a critical problem, making it very difficult designing a DPA with high enough PAE. Thus, a method of increasing the gain without increasing the chip size or compromising efficiency is highly sought-after.